A. Field of the Invention
This invention relates to digital waveform synthesis and, more particularly, to the deskewing and fine adjustment of output delay of digitally synthesized waveforms.
B. Description of the Prior Art
Analog phase-locked loops (PLLs) have found numerous applications in microprocessor clock generators in recent years. Duties performed by the PLLs include deskewing, duty-cycle control, and frequency multiplication. Recent trends in CMOS technology and in microprocessor design, however, make the use of analog PLLs as a decreasingly attractive solution when implementing microprocessor clock generators.
For example, analog PLLs typically use circuits that operate in saturation, such as current sources, current mirrors, charge pumps, and operational amplifiers. The current trend of rapid scaling-down of supply voltages in microprocessor design have increased the difficulty of implementing circuits that operate in saturation. Furthermore, the general incompatibility of analog design with digitally-oriented technologies, methodologies, and CAD tools also make implementation of analog PLL designs increasingly difficult. Thus, the use of exclusively digital techniques for implementing microprocessor clocks is desired.
A prior art technique for synthesizing clock waveforms is presented in U.S. Pat. No. 5,036,230, entitled "CMOS CLOCK-PHASE SYNTHESIZER," and assigned to the assignee of the present invention. The CMOS clock-phase synthesizer disclosed in U.S. Pat. No. 5,036,230, however, lacks abilities featured by the present invention including the ability to fine tune and deskew output waveforms. As a consequence, the resolution of the prior art CMOS clock-phase synthesizer is limited by the relatively large unit delay of the taps of the corresponding synchronous delay line.